Digital signal processors constitute an important aspect of signal processing in many high performance applications and end-user devices. Keeping the power dissipation as low as possible in a reconfigurable architecture that enables dynamic reconfiguration of hardware modules is quite a challenging task. This paper examines one approach towards low-power programmable DSPs that seeks to solve this problem by matching the model of computation of a given task with a well defined architectural granularity without adverse consequences on performance.
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