In this video I show the result of AM demodulation with a DSP floating point pipeline. Follow my work on Twitter: http://twitter.com/#!/jeriellsworth Faceboo…
Video Rating: 5 / 5
Part 2 – I show the progress of a homebew Software Defined Radio(SDR) or Direct Conversion receiver (DC). IQ signals now being generated correctly, but harmo…
Video Rating: 4 / 5
Great stuff. Will be interested to see how you do the DSP in the FPGA to
make it stand-alone.
Will you be releasing the full schematic and bom at some point?
The “data communication” at 4:20 sounds a lot like RTTY.
cool, so the fpga will connect to where the oscilator is? so you’ll have
modeled different oscilators in your fpga and it will be tuned by the fpga
as well or still by your computer?
I’m researching SDR on Yahoo – this looks good! My own idea is / was to
hack a DSO203 prtable ‘scope… convert IF using tha fast ADC, then
re-program the built in FPGA. Sound goes to PC via USB connector.
Will you add a TX function, or just leave it RX only?
What causes mirroring?
@Afrotechmods Yes. It will be part of the next Element14 video, but I think
this will evolve more past that video.
this is soooo cool!
Jeri, Do you have a Ham radio Call sign? if so what bands do yopu operate?
Tim W5TAH
Very nice progress since the last video. Someone commented that running the
LO through the FPGA — I think he meant as in implementing the I/Q divider
flipflops in the FPGA — would make a bunch of phase noise. Are flip-flops
in programmable logic necessarily phase noisy, or does it depend on how
they get laid out?
@PhattyMo Very fun.
how are the tiny little retangular resistors soldered to the board. Ive
heard of wave soldering but I wouldnt have thought thats how you do it at
home?
I didn’t know about WinRad prior to seeing your videos. Having visited
their site I noticed that there are newer versions. Is there any particular
reason you’re using 1.33 instead of a newer one?
I need a SDR receiver and want to learn on how to build one. I need
something that would cover 1 kHz to 30 MHz.
@rogercritchlow I’m working with an SDR design at the moment and have tried
using the Spartan-3A DCM to synthesise LO frequencies and because it’s a
delay locked loop, it has awful phase noise. The Spartan-6 has PLLs, which
may be better. I’ve since gone all the way and am using a DDS, driven by an
OCXO, and will be steering that using a GPS-derived 1pps signal (overkill
for one SDR, but handy if a network of independent receivers need to be
perfectly synchronised in frequency and phase)
you have a really big laptop…
@sonicase The FPGA has an integrated and adjustable PLL that I can use to
generate the local oscillator. I eventually want to remove the computer all
together.
Love it Jeri! I still have and use the Heathkit Grid Dip Meter that I built
as a kid in the late 70’s. I wonder how many people still know what they
are! The Johnson book on your desk is another real good one.
Simply brilliant. Watch out, you might get marriage proposals!
Very nice video. Thanks.
@wware I’m using the 74hc4066 version, which is faster.
I’m assembling a SDR kit from the UK that doesn’t use surface mount parts
and am not sure it’s working. I have used the Inphase only output of a
612 mixer of a DC receiver and connected it to Winrad and it works.
However, I don’t see signals from the SDR receiver and wonder if the
sensitivity is too low on the SDR kit. Any advise? I have a J310 rf
preamp but it doesn’t seem to work right with the SDR.
Thanks for the useful videos.
Your scared that you distroyed the 74HC4035 well as long as you use a
LM7805 your voltage cannot go higher than 5v and actually there is an item
called the bi-ssb exciter which uses the 74HC4035 without the 74AC74 it is
interesting to have a look at, not trying to diss your project which is
quite interesting in it’s own right.
You should get an AD9850 or AD9851 to replace the fixed-frequency crystal
oscillator. You can get them on preassembled modules for about $5/$12 each.
I saw you intend to use the PLL in the Spartan, but it might have pretty
bad stability (hmm, line-width?). It can be programed via parallel IO from
the FPGA.
I think one example of “insane” is pronouncing judgement on
something/someone to which you’ve never actually listened.
all the noise… from the carrier [turns on Rush Limbaugh]. HA HA, that was
funny.
If this kind of things keep going on, I have to warn you, that we might
have to erect statue to honor you in your lifetime.
Oh god why rush as an example.
I’m learning a lot from watching this project develop, Jeri. Thank you. 🙂
Rush is one insane bastard.
Very cool,Jeri! You are on the verge of becoming “one of us” which I and
others would gladly embrace! I could see you presenting this SDR receiver
at FDIM/Dayton. 73 Herb/WR9H
Would you happen to know how to build demodulation for various frequencies
being detected?
Jeri, If you’re even still messing about with SDR, using a “pro audio”
sound card and ASIO or WASAPI drivers can get the audio latency down to 5ms
or so on fast hardware with low DPC latency. Your FPGA will still have
lower latency, but 5ms is at least tolerable. Libraries like PortAudio make
it possible to use the PC as a good platform for audio-bandwidth QSD
experiments.
Very cool. I did some similar experimentation a few years ago. Initially I
tested the algorithms in java and using some broadband spectrum captures. I
did some testing in Xilinx’s ISE but did not get a chance to fully
implement it.
which rush does on a daily basis.
@hhdago I knew the FPGA would be faster, but I didn’t realize a quad core
laptop would have so much delay. Guess it’s all about the buffers.
Yeah I’m learning a lot as well! SDR is such a neat topic. Any plans for a
transmitter?
OK, this is creepy. Youtube was bufferng at one point, I was wondering what
the processing time difference between Software and FPGA would be, the
video continues and you show it.
oh no you played rush limbaugh through it, you have to burn it now
Now that’s homebrewing!
0:27 You’ve got mail!
@keenantims At some point I’d like to make a transmitter with the same
technique. It’s pretty much running the circuit backwards.
I think this is what you wanted it goes like this,
PMAX=32767;
NMAX=-PMAX;
TADJ=((PMAX+1)+(PMAX+1));
while(VALUE>PMAX)
{
VALUE-=TADJ;
}
while(VALUE